Solid-state image sensor and method of fabricating the same

ABSTRACT

There is provided a solid-state image sensor including a first region in which light is converted into electricity, and a second region composed of silicide. The second region at least partially forms a boarder area of the first region at a surface of the first region. The solid-state image sensor prevents occurrence of smear.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a solid-state image sensor and a methodof fabricating the same, and more particularly to a solid-state imagesensor capable of preventing occurrence of smear, and a method offabricating the same.

[0003] 2. Description of the Related Art

[0004]FIG. 1 illustrates a unit cell of a CMOS sensor which is an activeXY addrees type solid-state image sensor.

[0005] The illustrated unit cell is comprised of a p-type siliconsubstrate 10, a p-type well 12 formed in the p-type silicon substrate10, an n-type region 14 formed in the p-type well 12 and acting as aphotodiode, a gate insulating film 16 formed on a surface of the p-typesilicon substrate 10 and composed of silicon dioxide (SiO₂), a resetgate 18 formed on the gate insulating film 16 and composed ofpolysilicon, a reset drain region 20 composed of an n⁺ type region, afield oxide film 21 for electrical isolation between regions in each ofwhich a device is to be fabricated, and a light-impermeable film 22composed of metal and having an opening 23 through which light entersthe n-type region 14.

[0006] An interlayer insulating film and a wiring layer are formedbetween the light-impermeable film 22 and the n-type region 14 in whichlight is converted into electricity.

[0007] The n-type region 14 is electrically connected to a sourcefollower amplifier 24. As illustrated in FIG. 1, the source followeramplifier 24 is comprised of (a) a first MOS transistor 26 acting as aselector switch, (b) a second MOS transistor 28 having a sourceelectrically connected to a drain of the first MOS transistor 26, asource electrically connected to a voltage Vdd, and a gate electricallyconnected to the n-type region 14, (c) a third MOS transistor 29 actingas a load, and having a drain electrically connected to a source of thefirst MOS transistor 26, and a source electrically connected to avoltage Vss, and (d) an output terminal 30 electrically connected to asource of the first MOS transistor 26 and a drain of the third MOStransistor 29.

[0008] The CMOS sensor illustrated in FIG. 1 operates as follows.

[0009] First, a high pulse Φ_(R) is applied to the reset gate 18 tothereby cause the n-type region 14 acting as a photodiode, to have acertain potential. Then, a low pulse Φ_(R) is applied to the reset gate18 to thereby accumulate electric charges in a depletion layer whichelectric charges have been generated by converting light intoelectricity.

[0010] A potential of the photodiode 14 varies in accordance with thethus accumulated electric charges. Variation in the potential is outputthrough the output terminal 30 of the source follower amplifier 24.

[0011] In such a conventional CMOS sensor as illustrated in FIG. 1,since an interlayer insulating film and a plurality of wiring layers aresandwiched between the light-impermeable film 22 and the n-type regionor light-electricity converting region 14, the light-impermeable film 22is much spaced away from the n-type region 14. Hence, light 25diffracted due to diffraction effect of light having passed through theopening 23 reaches a boarder area of the light-electricity convertingregion 14, as illustrated in FIG. 1.

[0012] Thus, the conventional CMOS sensor is accompanied with a problemof so-called smear that light reaching a boarder of thelight-electricity converting region or n-type region 14 due todiffraction effect is converted into electricity to thereby generate afalse signal.

[0013] In addition, the thus generated false signal is trapped inadjacent light-electricity converting regions or in a diffusion layer ofthe source follower amplifier 24, resulting in another problem that aS/N ratio of image signals is degraded.

SUMMARY OF THE INVENTION

[0014] In view of the above-mentioned problem, it is an object of thepresent invention to provide a solid-state image sensor which is capableof preventing generation of smear or the above-mentioned false signal.It is also an object of the present invention to provide a method offabricating such a solid-state image sensor.

[0015] In one aspect of the present invention, there is provided asolid-state image sensor including a first region in which light isconverted into electricity, and a second region composed of silicide,the second region at least partially forming a boarder area of the firstregion at a surface of the first region.

[0016] The second region can interrupt light which would cause smear,from entering the region.

[0017] It is preferable that the solid-state image sensor is constitutedas a CMOS sensor or a CCD sensor.

[0018] It is preferable that the second region is composed of silicideof refractory metal.

[0019] There is further provided a solid-state image sensor including afirst region in which light is converted into electricity, a reset gateelectrode, a reset drain region, and a second region composed ofsilicide, the second region at least partially forming a boarder area ofthe first region at a surface of the first region.

[0020] There is still further provided a solid-state image sensorincluding a first region in which light is converted into electricity, areset gate electrode, a reset drain region, a second region composed ofsilicide, the second region at least partially forming a boarder area ofthe first region at a surface of the first region, and a third regioncomposed of silicide, the third region covering a surface of the resetdrain region therewith.

[0021] It is preferable that the second and third regions are formedfrom a common layer.

[0022] There is yet further provided a solid-state image sensorincluding a first region in which light is converted into electricity, alight-impermeable film having an opening situated above the firstregion, and a second region composed of silicide, the second region atleast partially forming a boarder area of the first region at a surfaceof the first region such that the second region interrupts diffractedlight coming through the opening, from entering the first region.

[0023] There is still yet further provided a solid-state image sensorincluding a first region in which light is converted into electricity, alight-impermeable film having an opening situated above the firstregion, a reset gate electrode, a reset drain region, and a secondregion composed of silicide, the second region at least partiallyforming a boarder area of the first region at a surface of the firstregion such that the second region interrupts diffracted light comingthrough the opening, from entering the first region.

[0024] There is further provided a solid-state image sensor including afirst region in which light is converted into electricity, alight-impermeable film having an opening situated above the firstregion, a reset gate electrode, a reset drain region, a second regioncomposed of silicide, the second region at least partially forming aboarder area of the first region at a surface of the first region suchthat the second region interrupts diffracted light coming through theopening, from entering the first region, and a third region composed ofsilicide, the third region covering a surface of the reset drain regiontherewith.

[0025] In another aspect of the present invention, there is provided amethod of fabricating a solid-state image sensor, including the steps of(a) forming a first region in which light is converted into electricity,in a silicon substrate, the first region having an electricalconductivity opposite to an electrical conductivity of the siliconsubstrate, and (b) forming a second region composed of silicide, thesecond region forming a boarder area of the first region at a surface ofthe first region.

[0026] For instance, the step (b) may be carried out by silicifying aboarder area of the first region or by depositing a refractory metalfilm and heating the refractory metal film.

[0027] It is preferable that the method further includes the step offorming a light-impermeable film having an opening situated above thefirst region.

[0028] There is further provided a method of fabricating a solid-stateimage sensor, including the steps of (a) forming a first region in whichlight is converted into electricity, in a silicon substrate, the firstregion having an electrical conductivity opposite to an electricalconductivity of the silicon substrate, (b) forming a reset gate on thesilicon substrate, (c) forming a reset drain region in the siliconsubstrate, the reset drain region having an electrical conductivityopposite to an electrical conductivity of the silicon substrate, and (d)forming a second region composed of silicide, the second region forminga boarder area of the first region at a surface of the first region.

[0029] It is preferable that the method further includes the step offorming a third region on a surface of the reset drain region, the thirdregion being composed of silicide, in which case, it is preferable thatthe second and third regions are simultaneously formed.

[0030] There is still further provided a method of fabricating asolid-state image sensor, including the steps of (a) forming a well in asilicon substrate, (b) forming a first region in which light isconverted into electricity, in the well, the first region having anelectrical conductivity opposite to an electrical conductivity of thewell, (c) forming a reset gate on the well, (d) forming a reset drainregion in the well, the reset drain region having an electricalconductivity opposite to an electrical conductivity of the well, and (e)forming a second region composed of silicide, the second region forminga boarder area of the first region at a surface of the first region.

[0031] The advantages obtained by the aforementioned present inventionwill be described hereinbelow.

[0032] In the solid-state image sensor in accordance with the presentinvention, the second region or silicified region is formed at a boarderof the first region or light-electricity converting region. As a result,there is no space into which diffracted light which would cause smear isincident. Hence, light which would cause smear is prevented fromentering the first region or light-electricity converting region.

[0033] Accordingly, it is now possible to prevent generation of a falsesignal to be generated by light entering a boarder area of the firstregion due to diffraction effect. In addition, it is also possible toprevent the thus generated false signal from being trapped in adjacentlight-electricity converting regions or in a diffusion layer of a sourcefollower amplifier, and thus, possible to prevent a S/N ratio of imagesignals from being degraded.

[0034] The above and other objects and advantageous features of thepresent invention will be made apparent from the following descriptionmade with reference to the accompanying drawings, in which likereference characters designate the same or similar parts throughout thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0035]FIG. 1 is a cross-sectional view of a unit cell of a conventionalCMOS sensor which is an active XY address type solid-state image sensor.

[0036]FIG. 2 is a cross-sectional view of a unit cell of a CMOS sensorin accordance with the first embodiment of the present invention.

[0037]FIGS. 3A to 3F are cross-sectional views of a unit cell,illustrating respective steps of a method of fabricating the unit cellillustrated in FIG. 2.

[0038]FIG. 4 is a cross-sectional view of a unit cell of a CMOS sensorin accordance with the second embodiment of the present invention.

[0039]FIGS. 5A and 5B are cross-sectional views of a unit cell,illustrating some of steps of a method of fabricating the unit cellillustrated in FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040]FIG. 2 illustrates a unit cell of a CMOS sensor in accordance withthe first embodiment of the present invention.

[0041] The illustrated unit cell is comprised of a p-type siliconsubstrate 10, a p-type well 12 formed in the p-type silicon substrate10, an n-type region or light-electricity converting region 14 formed inthe p-type well 12 and acting as a photodiode, a second region 32composed of silicide and formed on a boarder of the n-type region 14 ata surface of the n-type region 14, a gate insulating film 16 formed on asurface of the p-type silicon substrate 10 and composed of silicondioxide (SiO₂), a reset gate 18 formed on the gate insulating film 16and composed of polysilicon, a reset drain region 20 composed of an n⁺type region, a field oxide film 21 for electrical isolation betweenregions in each of which a device is to be fabricated, and alight-impermeable film 22 composed of metal and having an opening 23through which light enters the n-type region 14.

[0042] The unit cell in accordance with the first embodiment isstructurally different from the conventional unit cell illustrated inFIG. 1 in that the unit cell in accordance with the first embodiment isprovided with the second region 32 composed of silicide. The secondregion 32 may be formed, for instance, by silicifying the n-type region14 at a boarder thereof.

[0043] An interlayer insulating film and a wiring layer are formedbetween the light-impermeable film 22 and the n-type region 14 in whichlight is converted into electricity.

[0044] The n-type region 14 is electrically connected to a sourcefollower amplifier 24. As illustrated in FIG. 1, the source followeramplifier 24 is comprised of (a) a first MOS transistor 26 acting as aselector switch, (b) a second MOS transistor 28 having a sourceelectrically connected to a drain of the first MOS transistor 26, asource electrically connected to a voltage Vdd, and a gate electricallyconnected to the n-type region 14, (c) a third MOS transistor 29 actingas a load, and having a drain electrically connected to a source of thefirst MOS transistor 26, and a source electrically connected to avoltage Vss, and (d) an output terminal 30 electrically connected to asource of the first MOS transistor 26 and a drain of the third MOStransistor 29.

[0045] In accordance with the CMOS sensor, since the second region orsilicide region 32 is formed at a boarder of the n-type region orlight-electricity region 14, there is no angle between thelight-impermeable film 22 and the n-type region 14 for light which wouldcause smear, to enter the n-type region 14 due to diffraction.Accordingly, it is possible to prevent light which would cause smear,from entering the n-type region or light-electricity converting region14.

[0046] A method of fabricating the unit cell illustrated in FIG. 2 isexplained hereinbelow with reference to FIGS. 3A to 3F.

[0047] First, as illustrated in FIG. 3A, there is prepared a p-typesilicon substrate 10.

[0048] Then, as illustrated in FIG. 3B, field oxide films 21 are formedat a surface of the p-type silicon substrate 10 for electrical isolationamong regions in each of which a device is to be fabricated. Theadjacent field oxide films 21 are spaced away from each other by about0.6 μm.

[0049] Then, as illustrated in FIG. 3C, boron (B) is ion-implanted intothe p-type silicon substrate 10 to thereby form a p-type well 12 in thep-type silicon substrate 10. For instance, the p-type silicon substrate10 is implanted successively three times at 300 keV with doses of 1×10¹³boron cm⁻², at 100 keV with doses of 5×10¹² boron cm⁻² and at 60 keVwith doses of 2.5×10¹² boron cm⁻². The step of ion-implantation into thep-type silicon substrate 10 for forming the p-type well 12 may beomitted, if the p-type silicon substrate 10 had sufficient impurityconcentration without ion-implantation.

[0050] Then, as illustrated in FIG. 3D, a silicon dioxide film 34 havinga thickness of about 10 nm is formed on a surface of the p-type siliconsubstrate 10, and thereafter, a reset gate 18 is formed on the silicondioxide film 34. The reset gate 18 may be formed of polysilicon orpolycide having a two-layered structure comprising a polysilicon layerand a tungsten silicide layer.

[0051] Then, the p-type silicon substrate 10 is implanted at 70 keV withdoses of 1×10¹⁶ arsenic (As) cm⁻² to thereby form a reset drain region20 in the p-type well 12. The reset drain region 20 is formed of an n⁺type region.

[0052] Then, the reset drain region 20 is covered with a resist film,and thereafter, the p-type silicon substrate 10 is implanted at 150 keVwith doses of 1×10¹³ phosphorus (P) cm⁻² to thereby form alight-electricity converting region or n-type region 14.

[0053] Then, as illustrated in FIG. 3E, the silicon dioxide film 34 ispartially removed in an area where the light-electricity convertingregion 14 is to be silicified at a surface. That is, the silicon dioxidefilm 34 is removed at a boarder of the light-electricity convertingregion 14.

[0054] In the first embodiment, the silicon dioxide film 34 is formedalso as a gate insulating film 16. As an alternative, the silicondioxide film 34 may be removed except a portion situated below the resetgate 18 after formation of the reset gate 18, and a silicon dioxide filmmay be newly formed on the light-electricity converting region 14 by athickness of about 50 nm.

[0055] Then, as illustrated in FIG. 3F, titanium (Ti) is deposited bysputtering by a thickness of about 40 nm on the light-electricityconverting region 14 at a region where the silicon dioxide film 34 wasremoved. Thereafter, titanium is heated at 700 degrees centigrade for aminute to thereby form a silicide region 32.

[0056] Then, the silicon dioxide film 34 is entirely removed. A portionof the silicon dioxide film 34, situated below the reset gate 18, makesthe gate insulating film 16.

[0057] In the first embodiment, the silicide region 32 is composed oftitanium silicide. However, it should be noted that silicide of whichthe silicide region 32 is composed is not to be limited to titaniumsilicide. For instance, the silicide region 32 may be composed ofsilicide of refractory metal such as molybdenum (Mo), tungsten (W) andcobalt (Co).

[0058] Then, there are formed an interlayer insulating film, a wiringlayer, a light-impermeable film, and so on. Thus, there is completed theunit cell illustrated in FIG. 2.

[0059]FIG. 4 illustrates a unit cell of a CMOS sensor in accordance withthe second embodiment of the present invention.

[0060] In the first embodiment, the silicide region 32 is formed only ata boarder of the light-electricity converting region 14. However, itshould be noted that a silicide layer may be formed concurrently withthe silicide region 32 on the reset drain region 20 as a low-resistiveelectrode.

[0061] In the second embodiment, a silicide layer 36 is formed also onthe reset drain region 20. The unit cell in accordance with the secondembodiment, illustrated in FIG. 4, is structurally different from theunit cell in accordance with the first embodiment, illustrated in FIG.2, only in that the silicide layer 36 is formed on the reset drainregion 20. That is, a structure except the silicide layer 36 is commonin the unit cells in accordance with the first and second embodiments.Parts or elements that correspond to those of the unit cell illustratedin FIG. 2 have been provided with the same reference numerals in theunit cell illustrated in FIG. 4.

[0062] The formation of the silicide layer 36 on the reset drain region20 makes it possible to reduce a contact resistance.

[0063] A method of fabricating the unit cell illustrated in FIG. 4 isexplained hereinbelow with reference to FIGS. 5A and 5B.

[0064] The method is basically the same as the method of fabricating theunit cell illustrated in FIG. 2, but is different only in the formationof the silicon dioxide film 34.

[0065] The steps having been explained with reference to FIGS. 3A to 3Dare carried out in the same manner as the first embodiment.

[0066] Then, as illustrated in FIG. 5A, the silicon dioxide film 34 ispartially removed in an area where the light-electricity convertingregion 14 is to be silicified at a surface and an area on the resetdrain region 20. That is, the silicon dioxide film 34 is removed at aboarder of the light-electricity converting region 14, and on the resetdrain region 20.

[0067] Then, as illustrated in FIG. 5B, titanium (Ti) is deposited bysputtering by a thickness of about 40 nm on the light-electricityconverting region 14 at a region where the silicon dioxide film 34 wasremoved, and on the reset drain region 20. Thereafter, titanium isheated at 700 degrees centigrade for a minute to thereby form both asilicide region 32 at a boarder of the light-electricity convertingregion 14 and a silicide layer 36 on the reset drain region 20.

[0068] Then, the silicon dioxide film 34 is entirely removed. A portionof the silicon dioxide film 34, situated below the reset gate 18, makesthe gate insulating film 16.

[0069] Then, there are formed an interlayer insulating film, a wiringlayer, a light-impermeable film, and so on. Thus, there is completed theunit cell illustrated in FIG. 4.

[0070] In the first and second embodiments, a gate of the second MOStransistor 28 in the source follower amplifier 24 is electricallyconnected to the light-electricity converting region 14. As analternative, the gate may be electrically connected to the silicideregion 32 in place of the light-electricity converting region 14.

[0071] In the first and second embodiments, the solid-state image sensorin accordance with the present invention is applied to a CMOS sensor.However, those skilled in the art would readily understand that thesolid-state image sensor in accordance with the present invention may beapplied to a CCD sensor While the present invention has been describedin connection with certain preferred embodiments, it is to be understoodthat the subject matter encompassed by way of the present invention isnot to be limited to those specific embodiments. On the contrary, it isintended for the subject matter of the invention to include allalternatives, modifications and equivalents as can be included withinthe spirit and scope of the following claims.

[0072] The entire disclosure of Japanese Patent Application No.10-241322 filed on Aug. 27, 1998 including specification, claims,drawings and summary is incorporated herein by reference in itsentirety.

What is claimed is:
 1. A solid-state image sensor comprising: a firstregion in which light is converted into electricity; and a second regioncomposed of silicide, said second region at least partially forming aboarder area of said first region at a surface of said first region. 2.The solid-state image sensor as set forth in claim 1, wherein saidsecond region interrupts light which would cause smear, from enteringsaid region.
 3. The solid-state image sensor as set forth in claim 1,wherein said solid-state image sensor constitutes a CMOS sensor.
 4. Thesolid-state image sensor as set forth in claim 1, wherein saidsolid-state image sensor constitutes a CCD sensor.
 5. The solid-stateimage sensor as set forth in claim 1, wherein said second region iscomposed of silicide of refractory metal.
 6. A solid-state image sensorcomprising: a first region in which light is converted into electricity;a reset gate electrode; a reset drain region; and a second regioncomposed of silicide, said second region at least partially forming aboarder area of said first region at a surface of said first region. 7.The solid-state image sensor as set forth in claim 6, wherein saidsecond region interrupts light which would cause smear, from enteringsaid region.
 8. The solid-state image sensor as set forth in claim 6,wherein said second region is composed of silicide of refractory metal.9. A solid-state image sensor comprising: a first region in which lightis converted into electricity; a reset gate electrode; a reset drainregion; a second region composed of silicide, said second region atleast partially forming a boarder area of said first region at a surfaceof said first region; and a third region composed of silicide, saidthird region covering a surface of said reset drain region therewith.10. The solid-state image sensor as set forth in claim 9, wherein saidsecond and third regions are made of a common layer.
 11. The solid-stateimage sensor as set forth in claim 9, wherein said second regioninterrupts light which would cause smear, from entering said region. 12.The solid-state image sensor as set forth in claim 9, wherein saidsecond region is composed of suicide of refractory metal.
 13. Asolid-state image sensor comprising: a first region in which light isconverted into electricity; a light-impermeable film having an openingsituated above said first region; and a second region composed ofsilicide, said second region at least partially forming a boarder areaof said first region at a surface of said first region such that saidsecond region interrupts diffracted light coming through said opening,from entering said first region.
 14. The solid-state image sensor as setforth in claim 13, wherein said second region is composed of silicide ofrefractory metal.
 15. A solid-state image sensor comprising: a firstregion in which light is converted into electricity; a light-impermeablefilm having an opening situated above said first region; a reset gateelectrode; a reset drain region; and a second region composed ofsilicide, said second region at least partially forming a boarder areaof said first region at a surface of said first region such that saidsecond region interrupts diffracted light coming through said opening,from entering said first region.
 16. The solid-state image sensor as setforth in claim 15, wherein said second region is composed of silicide ofrefractory metal.
 17. A solid-state image sensor comprising: a firstregion in which light is converted into electricity; a light-impermeablefilm having an opening situated above said first region; a reset gateelectrode; a reset drain region; a second region composed of silicide,said second region at least partially forming a boarder area of saidfirst region at a surface of said first region such that said secondregion interrupts diffracted light coming through said opening, fromentering said first region; and a third region composed of silicide,said third region covering a surface of said reset drain regiontherewith.
 18. The solid-state image sensor as set forth in claim 17,wherein said second and third regions are made of a common layer. 19.The solid-state image sensor as set forth in claim 17, wherein saidsecond region is composed of silicide of refractory metal.
 20. A methodof fabricating a solid-state image sensor, comprising the steps of: (a)forming a first region in which light is converted into electricity, ina silicon substrate, said first region having an electrical conductivityopposite to an electrical conductivity of said silicon substrate; and(b) forming a second region composed of silicide, said second regionforming a boarder area of said first region at a surface of said firstregion.
 21. The method as set forth in claim 20, wherein said step (b)is carried out by silicifying a boarder area of said first region. 22.The method as set forth in claim 20, wherein said step (b) is carriedout by depositing a refractory metal film and heating said refractorymetal film.
 23. The method as set forth in claim 20, further comprisingthe step of forming a light-impermeable film having an opening situatedabove said first region.
 24. A method of fabricating a solid-state imagesensor, comprising the steps of: (a) forming a first region in whichlight is converted into electricity, in a silicon substrate, said firstregion having an electrical conductivity opposite to an electricalconductivity of said silicon substrate; (b) forming a reset gate on saidsilicon substrate; (c) forming a reset drain region in said siliconsubstrate, said reset drain region having an electrical conductivityopposite to an electrical conductivity of said silicon substrate; and(d) forming a second region composed of silicide, said second regionforming a boarder area of said first region at a surface of said firstregion.
 25. The method as set forth in claim 24, wherein said step (d)is carried out by silicifying a boarder area of said first region. 26.The method as set forth in claim 24, wherein said step (d) is carriedout by depositing a refractory metal film and heating said refractorymetal film.
 27. The method as set forth in claim 24, further comprisingthe step of forming a light-impermeable film having an opening situatedabove said first region.
 28. The method as set forth in claim 24,further comprising the step of forming a third region on a surface ofsaid reset drain region, said third region being composed of silicide.29. The method as set forth in claim 28, wherein said second and thirdregions are simultaneously formed.
 30. A method of fabricating asolid-state image sensor, comprising the steps of: (a) forming a well ina silicon substrate; (b) forming a first region in which light isconverted into electricity, in said well, said first region having anelectrical conductivity opposite to an electrical conductivity of saidwell; (c) forming a reset gate on said well; (d) forming a reset drainregion in said well, said reset drain region having an electricalconductivity opposite to an electrical conductivity of said well; and(e) forming a second region composed of silicide, said second regionforming a boarder area of said first region at a surface of said firstregion.
 31. The method as set forth in claim 30, wherein said step (e)is carried out by silicifying a boarder area of said first region. 32.The method as set forth in claim 30, wherein said step (e) is carriedout by depositing a refractory metal film and heating said refractorymetal film.
 33. The method as set forth in claim 30, further comprisingthe step of forming a light-impermeable film having an opening situatedabove said first region.
 34. The method as set forth in claim 30,further comprising the step of forming a third region on a surface ofsaid reset drain region, said third region being composed of silicide.35. The method as set forth in claim 30, where in said second and thirdregions are simultaneously formed.